1. Field of the Invention
The present invention relates to a disk array controller that includes a plurality of host directors, each controlling I/O (inut/output) requests from a host and executing I/O processing to or from disk devices, and a shared memory shared by those host directors and forming a disk cache.
2. Description of the Related Art
Recently, the installation of a cache memory on a disk array unit has become vital to increasing throughput. Because only a limited area of a disk array unit generally is accessed, copying a portion of the data to a cache memory ensures a quick response to a host computer.
Another technology that has been proposed in the related art is to balance the load by providing multiple directors each executing I/O processing. This configuration allows the host directors to concurrently process I/O requests from a plurality of hosts. In addition, disk directors, each of which executes physical disk access processing within a disk array unit independently, allow a high-priority host-to-cache data transfer and the cache-to-disk background processing to be executed asynchronously, thus increasing throughput.
The Japanese Patent Laid-Open Publication No. 2000-187617 (hereinafter called a first related art) discloses a cache memory management method, for use in a multi-director disk array unit, which allows multiple directors to execute processing concurrently without excluding each other even when multiple directors attempt to access the cache memory management area at the same time. FIG. 6 is a block diagram showing the disk array unit disclosed in the publication. FIG. 7 is a diagram showing the correspondence between logical disks used in this disk array unit and cache partitions. The method disclosed in this publication will be described with reference to those drawings.
A disk array 504 is connected to three hosts 501, 502, and 503 via three host directors 511, 512, and 513. The disk array 504 includes a cache memory 51, host directors 511, 512, and 513, physical disk units 525, and disk directors 531, 532, and 533 connected to the physical disk units 525. The cache memory 51 is divided logically into three partitions 521, 522, and 523. Each partition includes a management area, 5211, 5221, or 5231, and a cache area, 5212, 5222, or 5232, respectively.
Next, the operation will be described. First, assume that an access request is issued from the host 501 to logical disk 0. The host director 511, which uses cache partition 0 according to the correspondence shown in FIG. 7, operates on the cache management area 5211. While processing this request, the cache management area 5211 is exclusively controlled and other directors cannot access it. Assume that another access request is issued from the host 502 to logical disk 1 almost at the same time. The host director 512, which uses cache partition 1, must operate on the cache management area 5221. Because the cache management area 5221 is not exclusively controlled at this time, the director can start operation immediately.
Assume that the host 501 issues multiple write requests continuously. The host director 511 writes some into the cache partition 521, and the others into cache partition 522, according to the logical address. On the other hand, the disk director 531 writes data, which is written into the cache, onto the physical disk units 525 concurrently with the operation of the host director 511. At this time, even if the directors 511 and 531 attempt to access the cache management areas 5211 and 5221 almost at the same time, they can execute processing at the same time if they use different partitions.
As described above, because I/O requests from multiple hosts can be processed concurrently with no conflict in the operation of the cache management areas, the throughput is increased. This is because multiple cache partitions are completely independent and because, when operating on each management area, only the corresponding partition is exclusively controlled.
Recently, disk array units have become large because of an increase in the number of host connection ports, in the capacity of a disk drive and the maximum number of installed disk drives, and in the capacity of the disk cache. To implement such a large disk array unit, a technology has been developed to install multiple processors according to the number of host connection ports and the number of installed disk drives and to allow the shared memory to be used as the disk cache. This technology is called hereinafter a second related art. A disk cache refers to a device or a function that increases the speed of data transfer between a computer and a disk. In operation, data once read from a disk is accumulated in a memory and, the next time the same data is read, data is not read from the disk again but the data accumulated in the memory is used. This technology ensures both a sufficient throughput even in the multi-host connection configuration and scalability (extensibility) that allows host directors to be added as necessary.
FIG. 8 is a block diagram showing a disk array unit using such a shared memory method. The method will be described with reference to the drawing.
In this disk array unit, a host director 281 is connected to a host 121, and a host director 282 is connected to a host 122, respectively. A disk director 301 is connected to a disk drive 141, and a disk director 302 is connected to a disk drive 142, respectively. The host directors 281 and 282 and the disk directors 301 and 302 execute the concurrent operation while sharing a shared memory 18.
In this disk array unit, the time required to access the disk drives, which involves mechanical operations, is longer than the time required to access the shared memory 18. Therefore, the average performance may be increased by improving the cache hit ratio and by improving the response time at a cache hit time. The response time at a cache hit time is composed primarily of the host interface processing time, data transfer time, and shared memory control processing time. The host interface processing time and the data transfer time have already been reduced significantly by the fiber channel technology. Therefore, it is desired that the time for the shared memory control processing be also reduced. The fiber channel refers to an interface standard for connecting one computer to another or between a computer and a peripheral device with a coaxial cable or a fiber optic cable for high-speed data transfer.
When multiple commands are issued to an address and to the same address or another address near to it almost at the same time, a cache page conflict occurs. A cache page conflict puts the later processing in the wait state until the previous processing is finished because they are processed under exclusive control. Conventionally, there is no serious problem because a cache page conflict is rarely generated by I/O requests from separate hosts. However, when a host makes a multithread access, multiple commands issued from the same host cause a cache page conflict. In this case, the host issues multiple commands at a time to addresses that are near each other, expecting that the disk will transfer data continuously via the interface bus. However, because of a cache page conflict that occurs in the cache array, the cache page delivery processing must be executed after data is transferred and, therefore, the next data transfer cannot be started immediately. A division unit of a director process (processing unit) is called a “thread”. A multithread refers to a thread function corresponding to multiple processing requests (host processes) from the host.
FIG. 9 is a flowchart showing command processing in the second related art. The operation will be described below with reference to FIG. 8 and FIG. 9.
In response to commands from the hosts 121 and 122 (step 401), the host directors 281 and 282 operate on the management data in the shared memory 18 to occupy cache pages (step 402). After that, the directors start the data transfer (step 403) and wait until the data transfer is completed. When the data transfer is completed (step 404), the directors operate on the management data in the shared memory 18 to release the cache pages (step 405) and complete the commands (step 406).
FIG. 10 is a flowchart showing the processing that is performed when a cache page conflict occurs because two commands are received continuously from the host in the second related art. The operation will be described with reference to FIG. 8 and FIG. 10.
When command A is received and then command B is received (steps 501, 502), a cache page is occupied first for command A (step 503). Then, when the data transfer requested by command A is started (step 504), the processor becomes free until the transfer is completed and therefore an attempt is made to occupy a cache page for command B (step 505). However, because the cache page to be used is already occupied, command B is put in the conflict wait state. After that, the data transfer requested by command A is completed (step 506), the cache page occupied for command A is released (step 507), and command A is completed (step 508). At this time, command B can occupy the cache page (step 509). After that, command B continues processing (steps 510-513). As described above, from step 506 to step 510, the host interface remains unused except in step 508. This means that the host interface performance is not maximized.
As described above, in the second related art, a cache page conflict occurs when a plurality of commands are issued from the same host. On the other hand, in the first related art, although a cache page conflict between a plurality of commands from separate hosts may be prevented, a cache page conflict occurs when a plurality of commands are issued from the same host.